Designing 2D and 3D Network-on-Chip Architectures

Designing 2D and 3D Network-on-Chip Architectures

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This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.Linear block codes can be presented by their generator matrix G, which is of size k A— n, where k is the data word ... A Hamming code fulfills the rule 2(naˆ’k) a‰y n + 1, where n aˆ’ k is the number of check bits and n is the length of the code word.

Title:Designing 2D and 3D Network-on-Chip Architectures
Author: Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
Publisher:Springer Science & Business Media - 2013-10-08

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